On March 10, 2026, IBM and Lam Research announced a five-year collaboration to develop materials, processes and lithography techniques aimed at enabling logic devices below the 1 nanometer scale. The agreement frames the work around novel materials, advanced etch and deposition capabilities, and High-NA EUV lithography process development tied to IBM’s logic scaling roadmap.
The collaboration is expressly a five-year R&D agreement to extend logic scaling toward the sub-1nm node, building on more than a decade of prior work between the two organisations on earlier nodes and nanosheet architectures.
The technical focus areas are: new materials (including dry resists for High-NA EUV), advanced etch and deposition process capability, backside power-delivery approaches, and validation of full process flows for nanosheet and nanostack device architectures. The statement names IBM’s NY CREATES Albany NanoTech Complex and a set of Lam tool innovations that will be used in the work.
Both companies frame the effort as enabling “viable paths to production” for future logic devices rather than limited laboratory demonstrations; however, the releases do not set a commercial-production timetable or commit to specific manufacturing nodes beyond the research objective.
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Key technical points
• Material science and resist chemistry: High-NA EUV will require dry resist innovations and process recipes that behave predictably at higher doses and different optics. Lam’s releases call out Aether® dry resist work explicitly.
• Etch and deposition at angstrom precision: As vertical device complexity increases, etch selectivity and uniform deposition (including ALTUS® Halo deposition systems called out by Lam) will be essential to pattern transfer without damaging underlying layers.
• Backside power delivery and packaging interplay: The press materials mention backside power delivery, as part of the validation scope, integrating these electrical paths while preserving mechanical integrity and thermal dissipation is nontrivial and interacts with packaging roadmaps.
• Metrology and yield engineering: Achieving “viable paths to production” will require metrology innovations that can measure and control defects at sub-nanometer scales and provide the feedback loops needed for high yield. This is where the time and dollars will likely concentrate.
Milestones to watch
- Conference and media talks demonstrating measured pattern-transfer fidelity and resist performance under High-NA EUV exposure conditions.
- Demonstrations of full process flows on test wafers with published defect densities and yield metrics for nanosheet/nanostack stacks.
- Independent validation (academic, consortium or foundry partners) of backside power delivery approaches and package-level integration.
- Any joint papers or open technical disclosures that show the specific etch/deposition chemistries and the metrology methods used to control them.
Balanced assessment
The IBM Lam Research collaboration is a sensible, expected step for organisations attempting to push logic scaling past the current inflexion points. The partnership combines device-level research and production-scale tool expertise, the two capabilities that must converge for meaningful progress. That said, the hard questions remain in yield, throughput and commercial cost. For practitioners, the headline is useful; the technical community will need to see measured, reproducible results and process-qualified data before treating sub-1nm as a short-term practical roadmap item.
